1. Field of the Invention
The present invention relates to an A/D converter (analog-to-digital converter) used in various electronic devices and, more particularly, to a successive approximation type A/D converter formed into an integrated circuit.
2. Description of the Related Art
Generally, a successive approximation type A/D converter samples an analog voltage input, supplies a successive approximation control digital output from a successive approximation type control circuit to a local D/A converter to cause the D/A converter to generate a local analog voltage, compares the sampled and held analog voltage with the local analog voltage, and successively determines the value of each bit of an A/D conversion output on the basis of the relationship in magnitude between the compared voltages, thereby obtaining an A/D conversion output having a plurality of bits from the successive approximation type control circuit.
FIG. 1 shows a 3-bit A/D converter as a successive approximation type A/D converter. More specifically, reference symbols C1 and C2 respectively denote capacitors each having capacitance value C; C3, a capacitor having capacitance value 2C; C4, a capacitor having capacitance value 4C; A, an inverting amplifier; and SW, a switch. They constitute a voltage comparator. Reference numeral 1 denotes an analog input terminal; 2, a reference voltage terminal; and 3, a ground terminal. Reference symbols SL1 to SL4 denote selectors whose selective connection states are controlled by successive approximation control digital signals; and B, a successive approximation type control circuit having functions of successively outputting the successive approximation control digital signals, and determining each bit value of an A/D conversion output on the basis of the logical level of an output from inverting amplifier A.
The A/D-converting operation of the successive approximation type A/D converter will be described below. In a sample mode, switch SW is set in an ON state, and selectors SL1 to SL4 are controlled in a state for selecting analog input terminal 1. In this case, the potential at input terminal node N of inverting amplifier A becomes threshold voltage Vop. Assuming that an analog input voltage is represented by Vain, then charge Q8 stored in capacitors C1 to C4 can be given as: EQU Q8=(Vop-Vain).8C (1)
Subsequently, the mode is switched to an approximation mode, wherein switch SW is set in an OFF state, selectors SL1 to SL3 are controlled in a state for selecting ground terminal 3, and selector SL4 is controlled in a state for selecting reference voltage terminal 2. In this case, assuming that the potential at node N is represented by V1, then charge Q1 stored in capacitors C1 to C3, and charge Q2 stored in capacitor C4 are respectively given as: EQU Q1=(C+C+2C)V1 (2) EQU Q2=4C(V1-V.sub.R) (3)
Then, from the principle of conservation of charges, the following equation can be established at node N: EQU Q8=Q1+Q2 (4)
Therefore, substitutions of equations (1), (2), and (3) into equation (4) yield: ##EQU1## In equation (5), since V1&gt;Vop when1/2V.sub.R &gt;Vain, the output from inverting amplifier A goes to low level. Since V1&lt;Vop when 1/2V.sub.R &lt;Vain, the output from inverting amplifier A goes to high level. Successive approximation type control circuit B determines the value ("1" or "0") of an MSB (most significant bit) of a digital output to be output from successive approximation type control circuit B on the basis of the output from inverting amplifier A, and supplies a control signal to selectors SL2 to SL4 to perform an approximation operation corresponding to the next significant bit. The operation that successive approximation type control circuit B outputs a certain successive approximation control signal, and then determines the value of a certain bit on the basis of an output from the inverting amplifier is repeated a predetermined number of times (three times in the embodiment), thereby determining a 3-bit A/D conversion output.
In order to perform A/D conversion with high precision in the successive approximation type A/D converter described above, the charges stored in capacitors Cl to C4 in the approximation mode must be held. In this case, if a MOS transistor is used for the input stage of inverting amplifier A and an input signal is supplied to its gate, no problem is posed because of a very high input impedance. However, in inverting amplifier A whose input terminal is connected to node N, the problem of charge leakage caused by switch SW connected to node N is posed. A case will be taken into consideration, wherein as the switch SW, a CMOS analog switch comprising parallel-connected n- and p-channel transistors TN1 and TP1 having gates for respectively receiving complementary switch control signals .phi., and .phi. is used, as shown in, e.g., FIG. 2A. FIG. 2B shows an equivalent circuit of this analog switch. Referring to FIG. 2B, reference symbols D.sub.p and C.sub.p denote diodes and capacitors, respectively both of which have junctions with the source and drain of p-channel transistor TP1; and D.sub.N and C.sub.N, diodes and capacitors, respectively both of which have junctions with the drain and source of n-channel transistor TN1. In the case wherein the above-described A/D converter is operated at V.sub.DD voltage=5 V and analog input voltage Vain=0 to 5 V, if selector SL4 is set in a state for selecting reference voltage terminal 2 before selectors SL1 to SL3 are set in a state for selecting ground terminal 3 when the sample mode is switched to the approximation mode, potential V1 at node N becomes Vop+V.sub.R -Vain. In this case, normally, if sampling is performed at VOP=2.5V, V.sub.R =5V, and Vain =0V, then V1=7.5V. Diodes D.sub.p in FIG. 2B are rendered conductive, and the charges stored in capacitors C1 to C4 leak. For this reason, a proper A/D conversion output cannot be obtained. In contrast to this, if selectors SL1 to SL3 are set in a state for selecting ground terminal 3 before selector SL4 is set in a state for selecting reference voltage terminal 2 when the sample mode is switched to the approximation mode, potential V1 at node N becomes Vop-Vain. Thus, if sampling is performed at Vain=5, then V1 =-2.5V. As a result, diodes D.sub.N are rendered conductive, and the charges at node N leak. Similarly, a proper A/D conversion output cannot be obtained.
That is, in the conventional successive approximation type A/D converters described above, if analog input voltage Vain appears near V.sub.DD voltage or the ground potential, potential V1 at input terminal node N of inverting amplifier A for comparing voltages may be greatly changed to be higher than V.sub.DD power source voltage or to be lower than the ground potential because of the influences of a switching operation of the capacitor array (in other words, a D/A-converting operation for generating a local analog signal) when the sample mode is switched to the approximation mode. In this case, charge leakage occurs in switch SW, and hence a proper A/D-converting operation cannot be performed. For this reason, when the amplitude of analog input voltage Vain is equal to the power source voltage amplitude of the A/D converter, high-precision A/D conversion cannot be performed.